small discrete structures assignmentCreate a program that outputs a walk, trail, path, closed walk, circuit, and cycle of a given directed graph matrix. That matrix is to be hard coded as such…There are 4 vertices in this directed graph. We know that because there are 4 rows and 4 columns. If there is a 1 that means that the vertex on the left (you need to name them) has an arrow edge towards the vertex on the top. If there is a 2 that means there are two directed edges in the same direction going from the left vertex to the vertex on the top. If there is a 0 that means there are no edges from the vertex on the left to the top vertex.- Make sure to program the matrix in to your code.- Output an example of each, make sure they are labeled.Example of a directed graph matrix from your book. The red numbers around the matrix are the vertices. If there is a 0 it means there is no edge from the vertex on the right to the vertex on the top.Some RubricPreviousNextCOMPE 375 Embedded Systems Programming Outline § Memory organization basics § Examples for different memory types § Memory timing analysis for read/write § Example questions 2 COMPE 375 Embedded Systems Programming Memory Organization § N locations by M bits per location: § For n address bits, N = 2n locations § Ex: 20 address lines, 8 data bits per location § 20 address bits = 220 = 1M locations § 8 bits per location = 1M x 8 = 1MB (1 megabyte) § K = 210 = 1,024 § M = 220 = 1,048,576 § b=bit, B=Byte (8 bits) 3 COMPE 375 Embedded Systems Programming Memory Types § In the previous lecture, we saw that there are two basic types of memory: § Read-only memory (ROM) § Read-write memory (RAM) § Four commonly used memory types § ROM § Flash and EEPROM § Static RAM (SRAM) § Dynamic RAM (DRAM) 4 COMPE 375 Embedded Systems Programming Generic Pin Configuration § Each memory device has at least one chip select ( CS ) or chip enable ( CE ) or select ( S ) pin that enables the memory device § This enables read and/or write operations Source: Plusquellic 5 , Systems Design and Programming COMPE 375 Embedded Systems Programming Memory Chips § The number of address pins is related to the number of memory locations § Example sizes are 1K to 256M locations (depending on the device) § 1K à 10 pins, 256M à 28 pins § The data pins are typically bi-directional in read-write memories § The number of data pins is related to the size of the memory location § For example, an 8-bit wide (byte-wide) memory device has 8 data pins § Catalog listing of 1K X 8 indicate a byte addressable 8K memory 6 COMPE 375 Embedded Systems Programming Memory Chips § Each memory device has at least one control pin § For ROMs, an output enable ( OE ) or gate ( G ) is present § The OE pin enables and disables a set of tri-state buffers § For RAMs, a read-write ( R/W ) or write enable ( WE ) and read enable (OE ) are present § For dual control pin devices, it must be hold true that both are not 0 at the same time 7 COMPE 375 Embedded Systems Programming Example ROM Types § Non-volatile memory: Maintains its state when powered down § ROM : Factory programmed, cannot be changed. Older style § PROM : Programmable Read-Only Memory § Field programmable but only once. Older style § EPROM : Erasable Programmable Read-Only Memory § Reprogramming requires up to 20 minutes of high-intensity UV light exposure § EEPROM : Electrically Erasable Programmable ROM § Also called EAROM (Electrically Alterable ROM) and NOVRAM (NOnVolatile RAM) § Writing is much slower than a normal RAM § Used to store setup information, e.g. video card, on computer systems Source: Plusquellic, Systems Design and Programming 8 COMPE 375 Embedded Systems Programming Example EPROM Organization § Intel 2716 EPROM (2K X 8) Source: Plusquellic 9 , Systems Design and Programming COMPE 375 Embedded Systems Programming Example SRAM Organization § TI TMS 4016 SRAM (2K X 8): Source: Plusquellic 10 , Systems Design and Programming COMPE 375 Embedded Systems Programming Example DRAM Organization § TI TMS4464 DRAM (64K X 4): Source: Plusquellic 11 , Systems Design and Programming COMPE 375 Embedded Systems Programming Example DRAM Organization § There are 64K addressable locations which means it needs 16 address inputs, but it has only 8 § The row address (A 0 through A 7 ) are placed on the address pins and strobed into a set of internal latches § The column address (A 8 through A 15 ) is then strobed in using CAS § This is achieved by multiplexing: Source: Plusquellic, Systems Design and Programming 12 COMPE 375 Embedded Systems Programming Examples 1 Megabit Memories: SRAM and DRAM 13 COMPE 375 Embedded Systems Programming Memory Read Timing § Once the output data are valid, the address input cannot be changed immediately to start another read operation. This is because the device needs a certain amount of time, called read recovery time, to complete its internal operations before the next memory operation. § The sum of the access time and read recovery time is the memory read cycle time. This is the time needed between the start of a read operation and the start of the next memory cycle. 14 COMPE 375 Embedded Systems Programming Memory Write Timing § In addition to the address and chip enable inputs, an active low write pulse on the R/W line and the data to be stored must be applied during the write cycle. § The timing of data input is less restrictive and can be satisfied simply by holding the data input stable during the entire cycle. However, the application of the write pulse has two critical timing parameters: § The address setup time and the write pulse width § The address setup time is the time required for the address to stabilize and is the time that must elapse before the write pulse can be applied 15 COMPE 375 Embedded Systems Programming Memory Errors § Error detection § Parity, checksum, CRC (Cyclic Redundancy) § Error correction § Hamming codes, Block error correcting codes § Soft error § A transient error, that does not repeat § Hard error § An error that is permanent, reproducible 16 COMPE 375 Embedded Systems Programming Memory Error Checking § Parity checks: § Used to detect single bit errors in the memory § Odd parity § Parity bit maintains an odd # of 1’s in word § Even number of ones indicates an error § Even parity § Parity bit maintains an even # of 1’s in word § Odd number of ones indicates an error 17 COMPE 375 Embedded Systems Programming Example: Parity Checking § In an n-bit system: § Parity checking adds 1 bit for every n data bits § For EVEN parity, the (n+1)th bit is set to yield an even number of 1’s in all (n+1) bits § For ODD parity, the (n+1) th bit is set to make this number odd § Example even vs. odd parity checker: 18 COMPE 375 Embedded Systems Programming Block Parity § Horizontal and vertical parity bits § One parity bit for each row of bits § One parity bit for each column of bits § Single bit error will be detected § Row and column error indicates location § Complementing the bit fixes the error 19 COMPE 375 Embedded Systems Programming Example Using Even Parity § data: Horizontal (even) parity: § 1 0 1 1 p=1 odd horizontal parity+1 = even § 1 1 1 1 p=0 even horizontal parity § 1 0 0 1 p=0 even horizontal parity § 1 0 1 1 p=1 odd horizontal parity+1 = even § 0 1 1 0 <- The vertical parity for these 4 words 20 COMPE 375 Embedded Systems Programming Cyclic Redundancy Code (CRC) § CRC is based on a binary polynomial § Can be calculated using only shift & XOR § Better than checksum: § Detects data in wrong order or byte swapped § Detects missing or extra zeros in a block § Standardized polynomials, e.g. CCITT-16 § Standardized initial value of polynomial 21 COMPE 375 Embedded Systems Programming Checksum and Hamming § Hamming Code § Redundant code – extra code bits § Detects and corrects single bit errors § Checksum § Sum of all the bytes in a block of memory § Use LS 8 or 16 bits of the sum § Will not detect errors: § Extra/missing zeros, wrong order, swapped bytes 22 23 COMPE 375 Embedded Systems Programming Question 1 • What is the largest byte-wide SRAM that will fit in a 32 pin package? • 1M x 8 = 1MB = 8 Mb • 512K x 8 = 512KB = 4Mb • 256K x 8 = 256KB = 2Mb • 128K x 8 = 128KB = 1Mb 24 COMPE 375 Embedded Systems Programming Question 2 § What is the maximum number of bits that can be stored in a byte-wide ROM in a 32 pin package? § 2M x 8 = 2MB = 16Mb § 128K x 8 = 128KB = 1Mb § 1M x 8 = 1MB = 8Mb § 4M x 8 = 4MB = 32Mb 25 COMPE 375 Embedded Systems Programming Question 3 § Access time from address is: § The delay from a valid address to output enable active § The delay from enable active to valid memory read data § The delay from valid address to valid memory read data § The address access time when address must be held after the data is read 26 COMPE 375 Embedded Systems Programming Question 4 § Using 4Mx4 DRAMs, how many memory chips will be required to implement a 16 MB memory organized in 32 bit words? § 4 § 8 § 16 § 32 27 COMPE 375 Embedded Systems Programming Question 5 § A CRC code is: § An error detection and correction code § A checksum that detects data out of order § A block error detection code, that detects data which are out of order § A block error detection code which detects missing zeros and data which are out of order 28 COMPE 375 Embedded Systems Programming Question 6 § For a DRAM, what is the largest memory that can be packaged in a 24 pin package? § 32 Mb § 16 Gb § 64 Gb § 4 Gb 29
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